A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations

Summary, in English

This paper presents a 3rd-order, 3-bit continuous time (CT) Delta-Sigma modulator for an LTE radio receiver. By adopting a return-to-zero (RZ) pulse in the innermost DAC, the modulator shows a reduced sensitivity to loop-delay variations, and the additional loop delay compensation usually needed in CT modulators can be omitted. The modulator has been implemented in a 65nm CMOS process, where it occupies an area of 0.2mmx0.4mm. It achieves an SNR of 71dB and an SNDR of 69dB over a 9MHz bandwidth with an oversampling ratio of 16. Power consumption is 7.5mW from a 1.2V supply, for a figure-of-merit of 181fJ/conversion.

• Author: Mattias Andersson; Martin Andersson; Lars Sundström; Pietro Andreani
• Department/s: Department of Electrical and Information Technology; Departments at LTH; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2012
• Language: English
• Pages: 245-248
• Publication/Series: IEEE Asian Solid State Circuits Conference (A-SSCC), 2012
• Links: http://dx.doi.org/10.1109/IPEC.2012.6522671
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE Asian Solid-State Circuits Conference (ASSCC), 2012
• Conference date: 2012-11-12 - 2012-11-14
• Conference place: Kobe, Japan
• Status: Published
• Project: EIT_DRAGON Digital Radio Architectures Going Nanoscale
• Research group: Data converters & RF
• ISBN/ISSN/Other: ISBN: 978-1-4673-2468-8