Arithmetic reduction of adder leakage in nanoscale CMOS

Summary, in English

in today’s technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.

• Author: Peter Nilsson
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2008
• Language: English
• Pages: 717-720
• Publication/Series: 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: The 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008)
• Conference date: 2008-11-30 - 2008-12-03
• Conference place: Macao, China
• Status: Published
• Research group: Digital ASIC; Elektronikkonstruktion
• ISBN/ISSN/Other: ISBN: 978-1-4244-2341-5