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III/V Nanowire FETs for CMOS?

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Author

Summary, in English

III/V MOS transistors are currently attracting considerable attention. The main driving force is that the advantageous transport properties in III/V materials are expected to increase the drive current in the MOS transistors. Major challenges for the III/V MOS technologies include the growth of high-quality III/V materials oil Si Substrates and the control of the MOS interface. Using the nanowire technology, we have recently demonstrated enhancement mode operation of 50 nm L-g InAs nanowire wrap-gate transistors in a vertical configuration. They demonstrate a transconductance of 0.5 S/mm, an inverse sub-threshold slope of about 80 mV/dec., and an I-on/I-off ratio > 1000 for a drive voltage of V-d=0.5 V. These results show promise for the use of nanowires in CMOS applications.

Publishing year

2008

Language

English

Pages

741-743

Publication/Series

Sige, Ge, And Related Compounds 3: Materials, Processing, And Devices

Volume

16

Issue

10

Document type

Conference paper

Publisher

Electrochemical Society

Topic

  • Condensed Matter Physics
  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

3rd International SiGe, Ge, and Related Compounds Symposium

Conference date

2008-10-12 - 2008-10-17

Conference place

Honolulu, HI, United States

Status

Published

Research group

  • Nano

ISBN/ISSN/Other

  • ISSN: 1938-6737
  • ISSN: 1938-5862