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Accelerating vector operations by utilizing reconfigurable coprocessor architectures

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Author

Summary, in English

To enhance performance of digital signal processing tasks while keeping the flexibility of programmable solutions is a clear motivation for coprocessors implemented as reconfigurable hardware blocks. This paper investigates the applicability of such coprocessors targeting digital signal processing multi-media applications, initially in the field of speech and audio. A tightly coupled coprocessor architecture with reconfigurable datapath and a local memory system is presented. The coprocessor interacts with the main processor through asynchronous FIFOs. Three computational models that provide support for functionality of different granularities to be accelerated are investigated. A speedup in the range of 2 to 46 compared to processor execution is achieved for vector operations and larger kernels such as autocorrelation, block filtering and Fast Fourier Transform. © 2007 IEEE.

Publishing year

2007

Language

English

Pages

3972-3975

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Coprocessors
  • Reconfigurable coprocessors
  • Programmable solutions

Conference name

2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007

Conference date

2007-05-27 - 2007-05-30

Conference place

New Orleans, LA, United States

Status

Published

ISBN/ISSN/Other

  • ISSN: 2158-1525
  • ISSN: 0271-4310
  • CODEN: PICSDI