A VLSI architecture of the square root algorithm for V-BLAST detection

Summary, in English

MIMO has been proposed as an extension to 3G and Wireless LANs. As an implementation scheme of MIMO systems, V-BLAST is suitable for the applications with very high data rates. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to its low computational complexity and numerical stability. In this paper, the fixed-point implementation of the square root algorithm is analyzed, and a low complexity VLSI architecture is proposed. The proposed architecture is scalable for various configurations, and implemented for a 4 x 4 QPSK V-BLAST system in a 0.35 mu m CMOS technology. The chip core covers 9 mm(2) and 190 K gates. The detection throughput of the chip depends on the received symbol packet length. When the packet length is larger than or equal to 100 bytes, it can achieve a maximal detection throughput of 128 similar to 160 Mb/s at a maximal clock frequency of 80 MHz. The core power consumption, measured at 2.7 V and room temperature, is about 608 mW for 160 Mb/s data rate at 80 MHz, and 81 mW for 20 Mb/s at 10 MHz. The proposed architecture is shown to meet the requirements for emerging MIMO applications, such as 3G HSDPA and IEEE 802.11n.

• Author: Zhan Guo; Peter Nilsson
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2006
• Language: English
• Pages: 219-230
• Publication/Series: Journal of VLSI Signal Processing
• Volume: 44
• Issue: 3
• Links: http://dx.doi.org/10.1007/s11265-006-8536-8
• Document type: Journal article
• Publisher: Springer
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: wireless LAN; CORDIC; fixed-point; square root algorithm; MIMO; BLAST; ASIC; VLSI; HSDPA; 3G
• Status: Published
• Research group: Elektronikkonstruktion
• ISBN/ISSN/Other: ISSN: 0922-5773