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Test Scheduling for 3D Stacked ICs under Power Constraints

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Author

Summary, in English

This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.

Publishing year

2011

Language

English

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Design for Test (DfT)
  • Built in Self Test (BIST)
  • Test scheduling
  • Sessions
  • Test time
  • Test cost
  • 3D Stacked Integrated Circuit (SIC)
  • Through Silicon Via (TSV).

Conference name

2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)

Conference date

2011-01-06 - 2011-01-07

Conference place

Chennai, India

Status

Published

Research group

  • Digital ASIC