A 5GHz 90-nm CMOS all digital phase-locked loop

Summary, in English

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.

• Author: Ping Lu; Henrik Sjöland
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2009
• Language: English
• Pages: 65-68
• Links: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5357180&contentType=Conference+Publications&queryText%3DA+5GHz+90-nm+CMOS+all+digital+phase-locked+loop
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: RF; Digitally Controlled Oscillator (DCO); Phase Locked Loop (PLL); All Digital Phase-Locked Loop (ADPLL); Time-to-Digital Converter (TDC); CMOS
• Conference name: IEEE Asian Solid-State Circuits Conference (ASSCC), 2009
• Conference date: 2009-11-16 - 2009-11-18
• Conference place: Taiwan, Taiwan
• Status: Published
• Research group: Elektronikkonstruktion; Analog RF; Data converters & RF