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VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture

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Author

Summary, in English

This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Bluespec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.

Publishing year

2008

Language

English

Pages

1492-1497

Publication/Series

Proceedings of the 23rd Annual Acm Symposium on Applied Computing

Document type

Conference paper

Publisher

Association for Computing Machinery (ACM)

Topic

  • Computer Science

Keywords

  • Java processor
  • embedded systems
  • Bluespec

Conference name

Symposium on Applied Computing (SAC)

Conference date

0001-01-02

Status

Published

Research group

  • ESDLAB