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Low Complexity Soft-Output Signal Detector for Spatial-Multiplexing MIMO System

Author

Summary, in English

This paper presents a cost-efficient soft-output signal detector design solution targeting on the spatial-multiplexing MIMO system. The detector achieves low hardware cost and near-optimal detection performance based on the modification to the fixed-complexity sphere decoder (FSD) using several implementation-oriented algorithm-level improvements, which are early-pruning with polygon-shaped constraint, symbol-level bit-flipping, and l1-norm approximation. To evaluate the proposed method, we implement the MIMO detector in a 65-nm standard VT CMOS technology. The core area is 0.14 mm2 with 69 K equivalent gates, representing a 60% hardware-resource saving to the state of art in the open literature. The detecting throughput is up to 1.5Gb/s at 250-MHz clock frequency and 1.2-V supply. The normalized energy consumption of 36.4 pJ/b is shown to be the most energy-efficient design compared with other soft-output detectors.

Publishing year

2011

Language

English

Pages

1718-1722

Publication/Series

2011 IEEE 22ND INTERNATIONAL SYMPOSIUM ON PERSONAL INDOOR AND MOBILE RADIO COMMUNICATIONS (PIMRC)

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

22nd Annual IEEE symposium on Personal Indoor Mobile Radio Communications (PIMRC 2011)

Conference date

2011-09-11

Conference place

Toronto, Canada

Status

Published

Research group

  • Digital ASIC

ISBN/ISSN/Other

  • ISBN: 978-1-4577-1348-4