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Design considerations of a floating-point ADC with embedded S/H

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Author

  • Johan Piper
  • Jiren Yuan

Summary, in English

This paper presents the implementation and test results of a 10+5 bit 50 MS/s floating-point ADC, along with the design considerations. The combination of resistive weighting with identical chopped gain stages proved successful in gain, delay and offset matching. It demonstrated that the input referred thermal noise of the gain stages needs to aim for 15 bits, while the rest of the requirements such as channel matching (gain, delay, offset) and settling time need only 10 bits. The channel selecting logic has a serious impact on the ADC distortion, especially at high frequencies. For this reason, a robust channel selecting logic is suggested

Publishing year

2005

Language

English

Pages

6166-6169

Publication/Series

IEEE International Symposium on Circuits and Systems (ISCAS)

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • resistive weighting
  • chopped gain stages
  • input referred thermal noise
  • channel matching
  • ADC distortion
  • settling time
  • delay
  • floating-point ADC
  • embedded S/H
  • offset matching
  • robust channel selecting logic

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS), 2005

Conference date

2005-05-23 - 2005-05-26

Conference place

Kobe, Japan

Status

Published

ISBN/ISSN/Other

  • ISBN: 0-7803-8834-8