Design of coarse-grained dynamically reconfigurable architecture for DSP applications
Author
Summary, in English
This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.
Publishing year
2009
Language
English
Pages
338-343
Publication/Series
International Conference on Reconfigurable Computing and FPGAs
Links
- Publication in Lund University research portal
- http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5382079&matchBoolean%3Dtrue%26searchField%3DSearch_All%26queryText%3D(Design+of+coarse-grained+dynamically+reconfigurable+architecture+for+DSP+applications)
- http://dx.doi.org/10.1109/ReConFig.2009.49
Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- Coarse-grained reconfigurable architecture
- FFT.
- Dynamically reconfigurable cell array
- Hybrid interconnect
Conference name
2009 International Conference on ReConFigurable Computing and FPGAs
Conference date
2009-12-09 - 2009-12-11
Conference place
Cancun, Mexico
Status
Published
Research group
- Digital ASIC
ISBN/ISSN/Other
- ISBN: 978-0-7695-3917-1