A low-complexity VLSI architecture for square root MIMO detection

Summary, in English

Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved

• Author: Zhan Guo; Peter Nilsson
• Department/s: Departments at LTH; Department of Electrical and Information Technology
• Publishing year: 2003
• Language: English
• Pages: 304-309
• Publication/Series: Proceedings of the IASTED International Conference on Circuits, Signals, and Systems
• Document type: Conference paper
• Publisher: ACTA Press
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: multiple-input multiple-output; square root algorithm; power consumption; finite word length analysis; VirtexE series Xilinx FPGA; field programmable gate arrays; 4-transmit antennas; quarter phase-shift keying; 4-receive antennas; QPSK modulation; MIMO detection; VLSI architecture; very large scale integration
• Conference name: IASTED International Conference on Circuits, Signals and Systems, 2003
• Conference date: 2003-05-19 - 2003-05-21
• Conference place: Cancun, Mexico
• Status: Published
• Research group: Elektronikkonstruktion
• ISBN/ISSN/Other: ISBN: 0-88986-351-2