A Reconfigurable Pipelined ADC in 0.18 um CMOS

Summary, in English

A reconfigurable pipelined A/D converter has been implemented in a 0.18 mu m RF-CMOS process. The ADC has eight configurations with a top performance of 10 bits resolution at 80 MSPS consuming 94mW. The reconfigurability is achieved by combining the cyclic and pipelined ADC architectures giving it a low level of complexity. In the conventional pipeline mode, the measured SFDR is 69 dBFS and the SNDR is 56.5 dBc for a 1.54 MHz single sinusoid tone input.

• Author: Martin Andersson; Karl Norling; Andreas Dreyfert; Jiren Yuan
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2005
• Language: English
• Pages: 326-329
• Publication/Series: 2005 Symposium on VLSI Circuits, Digest of Technical Papers
• Links: http://dx.doi.org/10.1109/VLSIC.2005.1469397
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: Symposium on VLSI Circuits
• Conference date: 2005-06-16 - 2005-06-18
• Conference place: Kyoto, Japan
• Status: Published
• ISBN/ISSN/Other: ISBN: 4-900784-01-X