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A scalable pipelined complex valued matrix inversion architecture

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Author

Summary, in English

This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R<sup>-1</sup> with Q. We show that traditional triangular array architectures employing O(n<sup>2</sup>) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixed-point representation. The hardware implementation will be used as a core processor in a real-time smart antenna system

Publishing year

2005

Language

English

Pages

4489-4492

Publication/Series

IEEE International Symposium on Circuits and Systems (ISCAS)

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • squared Givens rotations algorithm
  • recurrence algorithm
  • triangular matrix
  • linear array architecture
  • smart antenna systems
  • fixed-point representation arithmetic operations
  • 12 bit
  • QR-factorization
  • complex valued matrix inversion
  • FPGA implementation
  • scalable pipelined architecture

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS), 2005

Conference date

2005-05-23 - 2005-05-26

Conference place

Kobe, Japan

Status

Published

ISBN/ISSN/Other

  • ISBN: 0-7803-8834-8