Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time ΣΔ ADC

Summary, in English

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-mum BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (SigmaDelta) ADC has 84-dB dynamic range over a total bandwidth of +/-135 kHz for an active area of 0.4 mm(2). Hence, most of the channel filtering is realized in a CMOS IC where digital processing-is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm(2).

• Author: Y Le Guillou; O Gaborieau; P Gamand; M Isberg; P Jakobsson; L Jonsson; D Le Deaut; H Marie; Sven Mattisson; L Monge; T Olsson; S Prouet; T Tired
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2005
• Language: English
• Pages: 403-411
• Publication/Series: IEEE Journal of Solid-State Circuits
• Volume: 40
• Issue: 2
• Links: http://dx.doi.org/10.1109/JSSC.2004.841036
• Document type: Journal article
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: IIP2; GSM; GPRS; front-end; EDGE; direct conversion; dc offset; continuous time; analog-to-digital conversion; BiCMOS; low-noise; amplifier (LNA); mixer; self-mixing; sigma-delta (Sigma Delta)
• Status: Published
• ISBN/ISSN/Other: ISSN: 0018-9200