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Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling

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Author

  • Soheil Samii
  • Mikko Selkälä
  • Erik Larsson
  • Krishnendu Chakrabarty
  • Zebo Peng

Summary, in English

Concurrent testing of the cores in a core-based system- on-chip reduces the test application time but increases the test power consumption. Power models, test architecture design, and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is simple for a scheduling algorithm to handle but is pessimistic. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding test architecture design and scheduling algorithm. The power model takes into account the switching activity in the scan chains caused by both the test stimuli and the expected test responses during scan-in, launch-and-capture, and scan-out. Furthermore, we allow a unique power model per wrapper-chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Through circuit simulations on ISCAS'89 benchmarks, we demonstrate a high correlation between the real test power dissipation and our cycle-accurate test power model. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be reduced substantially by using the proposed cycle-accurate test power model.

Publishing year

2008

Language

English

Pages

973-977

Publication/Series

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume

27

Issue

5

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Power constraint
  • Power estimation
  • Scan chain
  • System-on-chip (SoC)
  • Test architecture design
  • Test power
  • Test scheduling

Status

Published

ISBN/ISSN/Other

  • ISSN: 0278-0070