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SOC Test Time Minimization Under Multiple Constraints

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Author

Summary, in English

In this paper, we propose a SOC (system-on-chip) test scheduling technique that minimizes the test application time while considering test power limitations and test conflicts. The test power consumption is important to consider since exceeding the system's power limit might damage the system. Our technique takes also into account test conflicts that are due to cross-core testing (testing of interconnections), unit testing with multiple test sets, hierarchical SOCs where cores are embedded in cores, and the sharing of test access mechanism (TAM). Our technique handles these conflicts as well as precedence constraints, which is the order in which the tests has to be applied. We have implemented our algorithm and performed experiments, which shows the efficiency of our approach.

Publishing year

2003

Language

English

Pages

312-317

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • SOC
  • system-on-chip
  • test scheduling
  • power limitations
  • test conflicts
  • test access mechanisms

Conference name

12th IEEE Asian Test Symposium ATS 2003

Conference date

2003-11-16 - 2003-11-19

Status

Published

ISBN/ISSN/Other

  • ISSN: 1081-7735
  • ISBN: 0-7695-1951-2