The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

Scheduling Tests for Stacked 3D Chips under Power Constraints

På svenska

Author

Summary, in English

This paper addresses test application time (TAT)

reduction for core-based stacked 3D chips. In contrast to the

traditional method of testing non-stacked chips where the same

test schedule is applied both at wafer test and at final test, stacked

3D chips need a pre-bond test schedule for each individual chip

and a different post-bond test schedule where all chips are jointly

tested. We consider a system of core-based chips where each core

is tested with a dedicated Built-In Self-Test (BIST) engine and

define an algorithm that defines each pre-bond test schedule and

the post-bond test schedule such that the overall TAT is

minimized and power constraints are met. The cost due to the

number of BIST control-lines is also taken into account.

Experiments with the proposed algorithm show significant savings

in TAT.

Publishing year

2010

Language

English

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Built in Self Test (BIST)
  • Design for Test (DfT)
  • Test scheduling
  • Sessions
  • Test time
  • Test cost
  • 3D Stacked Integrated Circuit (SIC)
  • Through Silicon Via (TSV).

Conference name

Swedish SoC Conference 2010

Conference date

2010-05-03 - 2010-05-04

Conference place

Kolmården, Sweden

Status

Published

Research group

  • Digital ASIC