Architectures and arithmetic for low static power consumption in nanoscale CMOS
Author
Summary, in English
This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative power ratio is strongly dependent on the used word length, i.e. the gain in power ratio is larger for longer word lengths. A static power ratio at 0.48 is shown for the bit-serial FIR-filter and a power ratio at 0.11 is shown in the arithmetic part of the FIR-filter. The static power ratio in the IIR-filter is 0.36 in the bit-serial filter and 0.06 in the arithmetic part of the filter. It is also shown that the use of storage, such as registers, relatively the arithmetic part affects the power ratio. The relatively lower power consumption in the IIR-filter compared to the FIR-filter is due to the lower use of registers.
Publishing year
2009
Language
English
Publication/Series
VLSI Design
Issue
Article ID 749272
Document type
Journal article
Publisher
Hindawi Limited
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
Research group
- Digital ASIC
ISBN/ISSN/Other
- ISSN: 1065-514X