The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

InAs WRAP-gate nanowire transistors

På svenska

Author

Summary, in English

InAs nanowire wrap-gate transistors have been fabricated in a vertical geometry using matrices of 11×11 nanowires. The fabrication process is based on conventional and scalable technologies that are adopted for the nanowire transistors. A SiN<sub>x</sub> layer is used as gate dielectric and a wrap-gate of 80 nm gate length is formed. These transistors show good DC characteristics with drive currents above 1 mA and a transconductance of 0.28 mS at V<sub>sd</sub>=0.5V. The transistors operate in depletion mode. © 2007 IEEE.

Publishing year

2007

Language

English

Pages

527-529

Publication/Series

Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Condensed Matter Physics

Keywords

  • Drive currents
  • Nanowire transistors
  • WRAP-gate nanowire
  • Scalable technologies

Conference name

IPRM'07: IEEE 19th International Conference on Indium Phosphide and Related Materials

Conference date

2007-05-14 - 2007-05-18

Conference place

Matsue, Japan

Status

Published

ISBN/ISSN/Other

  • ISSN: 1092-8669
  • CODEN: CPRMEG