A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's

Summary, in English

This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 μm standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage

• Author: Peter Nilsson; Mats Torkelson
• Department/s: Department of Electrical and Information Technology; Departments at LTH
• Publishing year: 1996
• Language: English
• Pages: 700-706
• Publication/Series: IEEE Journal of Solid-State Circuits
• Volume: 31
• Issue: 5
• Links: http://dx.doi.org/10.1109/4.509852
• Document type: Journal article
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• Research group: Elektronikkonstruktion
• ISBN/ISSN/Other: ISSN: 0018-9200