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Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates

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Author

Summary, in English

We report on InAs enhancement-mode field-effect transistors integrated directly on Si substrates. The transistors consist of vertical InAs nanowires, grown on Si substrates without the use of metal seed particles, and they are processed with a 50-nm-long metal wrap gate and high-kappa gate dielectric. Device characteristics showing enhancement-mode operation are reported. The output characteristics are asymmetric due to the band alignment and band bending at the InAs/Si interface. The implemented transistor geometry can therefore also serve as a test structure for investigating the InAs/Si heterointerface. From temperature-dependent measurements, we deduce an activation energy of about 200 meV for the TnAs/Si conduction band offset.

Publishing year

2008

Language

English

Pages

3037-3041

Publication/Series

IEEE Transactions on Electron Devices

Volume

55

Issue

11

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Condensed Matter Physics
  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • nanowires (NWs)
  • Field-effect transistor (FET)
  • InAs
  • on Si
  • III-V
  • wrap gate

Status

Published

Research group

  • Nano

ISBN/ISSN/Other

  • ISSN: 0018-9383