An Integrated System-on-Chip Test Framework
Author
Summary, in English
In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.
Publishing year
2008
Language
English
Pages
439-454
Publication/Series
[Host publication title missing]
Links
Document type
Book chapter
Publisher
Springer
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- testing
- system-on-chip
- SOC
- framework
- integrated testing
Status
Published
ISBN/ISSN/Other
- ISBN: 978-1-4020-6487-6