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Amplifier Design Using Vertical InAs Nanowire MOSFETs

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Author

Summary, in English

In this paper, an amplifier design using ballistic vertical InAs nanowire (NW) transistors is investigated, focusing on a basic common-source amplifier. The maximum power gain at 90 GHz is evaluated for different NW transistor architectures together with the power dissipation. The linearity of the amplifier is evaluated by estimating the IIP3 and 1-dB compression points. Furthermore, the impact of the parasitic capacitances and resistances is quantified and it is demonstrated that the gain may be increased by a cascode design. It is concluded that a power gain exceeding 20 dB at 90 GHz may be achieved by a common-source amplifier based on an InAs NW transistor architecture. A power consumption below 1 mW is possible, while still maintaining a high power gain. Furthermore, IIP3 exceeding 10 dBm is predicted. The combination of these qualities makes the NW transistor architecture an attractive prospect for low-power amplifiers at millimeter wave frequencies.

Publishing year

2016-06-01

Language

English

Pages

2353-2359

Publication/Series

IEEE Transactions on Electron Devices

Volume

63

Issue

6

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Amplifier
  • InAs
  • nanowires (NWs)
  • transistor

Status

Published

ISBN/ISSN/Other

  • ISSN: 0018-9383