Sizing of Dual-V-T Gates for Sub-V-T Circuits

Summary, in English

This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.

• Author: Babak Mohammadi; Syed Muhammad Yasser Sherazi; Joachim Rodrigues
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2012
• Language: English
• Publication/Series: 2012 IEEE Subthreshold Microelectronics Conference (SubVT)
• Links: http://dx.doi.org/10.1109/SubVT.2012.6404305
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE Subthreshold Microelectronics Conference (SubVT)
• Conference date: 2012-10-09 - 2012-10-10
• Status: Published
• ISBN/ISSN/Other: ISBN: 978-1-4673-1586-9