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Test Planning for 3D SICs using ILP

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Author

Summary, in English

In this paper we propose a test planning scheme for corebased

3D stacked integrated circuits where the total test cost for wafer

sort of each individual chip and the test cost of the complete stack

at package test is minimized. We use an Integer Linear Programming

(ILP) model to find the optimal test cost, which is given as the weighted

sum of the test time and the test access mechanism (TAM). As ILP is

time consuming, we use a scheme to bound the test time and the TAM

such that the search space is reduced. The proposed bounding scheme

and the ILP model were applied on several ITC’02 benchmarks and the

results show that optimal solutions were obtained at low computation

time.

Publishing year

2013

Language

English

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Design for Test (DfT)
  • IEEE 1500
  • Test architecture
  • Test scheduling
  • Sessions
  • Test time
  • Test cost
  • 3D Stacked Integrated Circuit (SIC)
  • Through Silicon Via (TSV)
  • Integer Linear Programming (ILP).

Conference name

Swedish System-On-Chip Conference (SSoCC), 2013

Conference date

2013-05-06 - 2013-05-07

Conference place

Ystad, Sweden

Status

Published