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A coarse-grained dynamically reconfigurable architecture for digital signal processing

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Author

Summary, in English

This paper presents design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing the separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible static mapping of arbitrary applications, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality is demonstrated by mapping a radix 22 FFT processor reconfigurable between 32 and 1,024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to an ordinary DSP solution.

Publishing year

2009

Language

English

Publication/Series

9th Swedish System-On-Chip Conference

Document type

Conference paper

Publisher

Swedish Chapter of IEEE Solid-State Circuits Society (SSCS)

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • DSP
  • CGRA

Conference name

Swedish System-on-Chip Conference 2009 (SSoCC'09)

Conference date

2009-05-04 - 2009-05-05

Conference place

Arild, Sweden

Status

Published

Research group

  • Digital ASIC