RF Characterization of Vertical Wrap-Gated InAs/High-κ Nanowire Capacitors

Summary, in English

This paper presents RF as well as low-frequency capacitance–voltage (C–V) characterization of vertical wrap-gated InAs/high-κ nanowire MOS capacitors. A full equivalent circuit model for traps is used to fit the low-frequency C–V characteristics, from which the interface trap density (Dit) and border trap density (Nbt) are evaluated separately. The results show comparable Nbt but far lower Dit (<10E12 eV−1cm−2 near the conduction band edge) for a nanowire MOS gate-stack compared with planar references. In the RF domain, the influence of nanowire series resistances become significant, and by introducing

a distributed RC-model, the nanowire resistivity (ρnw) is evaluated from the capacitance data as a function of the gate bias. An ON/OFF ρnw ratio of 10E−2 is obtained for the best device. Using the measured data, the quality factor is finally evaluated both for fabricated and ideal capacitors. The results agree well with simulated data.

• Author: Jun Wu; Kristofer Jansson; Aein Shiri Babadi; Martin Berg; Erik Lind; Lars-Erik Wernersson
• Department/s: Department of Electrical and Information Technology; Solid State Physics; NanoLund: Centre for Nanoscience
• Publishing year: 2016
• Language: English
• Pages: 584-589
• Publication/Series: IEEE Transactions on Electron Devices
• Volume: 63
• Issue: 2
• Links: http://dx.doi.org/10.1109/TED.2015.2506040
• Document type: Journal article
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering; Condensed Matter Physics
• Keywords: trap density.; RF; resistivity; quality factor; nanowire; InAs; high-κ; Capacitance–voltage (C–V)
• Status: Published
• Project: EIT_WWW Wireless with Wires
• Research group: Nano
• ISBN/ISSN/Other: ISSN: 0018-9383