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Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures

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Author

  • Christophe Wolinski
  • Krzysztof Kuchcinski
  • Jürgen Teich
  • Frank Hannig

Summary, in English

n this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized significantly (62% in average).

Publishing year

2008

Language

English

Pages

391-396

Publication/Series

2008 International Conference on Field Programmable Logic and Applications

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Computer Science

Conference name

International Conference on Field Programmable Logic and Applications (FPL)

Conference date

2008-09-08 - 2008-09-10

Conference place

Heidelberg, Germany

Status

Published

Research group

  • ESDLAB

ISBN/ISSN/Other

  • ISBN: 978-1-4244-1960-9