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NoC-based CSP support for a Java chip multiprocessor

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Author

Summary, in English

In this paper we examine the idea of implementing communicating sequential processes (CSP) constructs on a Java embedded chip multiprocessor (CMP). The approach is intended to reduce the memory bandwidth pressure on the shared memory, by employing a dedicated network-on-chip (NoC). The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. A CMP architecture of three processors is implemented and tested on an FPGA, showing a 15% increase in device area without performance penalties. Compared to shared memory-based communication, our NoC-based solution is between 2.3 and 11.5 times faster, depending on the communication and memory configuration.

Publishing year

2010

Language

English

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Computer Science

Keywords

  • NoC
  • CSP
  • multiprocessor
  • Java

Conference name

NORCHIP Conference, 2010

Conference date

2010-11-15 - 2010-11-16

Conference place

Tampere, Finland

Status

Published

Research group

  • ESDLAB

ISBN/ISSN/Other

  • ISBN: 978-1-4244-8972-5