A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

Summary, in English

A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.

• Author: Ying Wu; Ping Lu; Robert Bogdan Staszewski
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2015
• Language: English
• Pages: 95-98
• Publication/Series: 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
• Links: http://dx.doi.org/10.1109/RFIC.2015.7337713
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015
• Conference date: 2015-05-17 - 2015-05-19
• Conference place: Phoenix, Arizona, United States
• Status: Published
• ISBN/ISSN/Other: ISBN: 978-1-4799-7642-3