New single clock CMOS latches and flipflops with improved speed and power savings

Summary, in English

New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.

• Author: Jiren Yuan; Christer Svensson
• Department/s: Department of Electrical and Information Technology
• Publishing year: 1997
• Language: English
• Pages: 62-69
• Publication/Series: IEEE Journal of Solid-State Circuits
• Volume: 32
• Issue: 1
• Links: http://dx.doi.org/10.1109/4.553179
• Document type: Journal article
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• ISBN/ISSN/Other: ISSN: 0018-9200