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Test Planning and Test Access Mechanism Design for 3D SICs

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Author

Summary, in English

In this paper we propose a scheme for test planning

and test access mechanism (TAM) design for stacked integrated

circuits (SICs) that are designed in a core-based manner. Our

scheme minimizes the test cost, which is given as the weighted

sum of the test time and the TAM width. The test cost is evaluated

for a test flow that consists of a wafer sort test of each individual

chip and a package test of the complete stack of chips. We

use an Integer Linear Programming (ILP) model to find the optimal

test cost. The ILP model is implemented on several designs

constructed from ITC’02 benchmarks. The experimental results

show significant reduction in test cost compared to when using

schemes, which are optimized for non-stacked chips.

Publishing year

2014

Language

English

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

Swedish System on Chip Conference (SSoCC)

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Design for Test (DfT)
  • Test architecture
  • IEEE 1500
  • Test scheduling
  • Sessions
  • Test time
  • Test cost
  • 3D Stacked Integrated Circuit (SIC)
  • Through Silicon Via (TSV).

Conference name

Swedish System on Chip Conference (SSoCC), 2014

Conference date

2014-05-12 - 2014-05-13

Conference place

Vadstena, Sweden

Status

Published

Research group

  • Digital ASIC