A 0.7 - 3.7 GHz Six Phase Receiver Front-End With Third Order Harmonic Rejection
Author
Summary, in English
This paper presents a highly linear receiver frontend
operating from 700 MHz to 3.7 GHz with 3rd order harmonic
rejection. It consists of a complementary low noise transconductance
amplifier with capacitive cross coupling and negative gm
current sources, a six phase current-mode passive mixer, and
baseband transimpedance amplifiers providing programmable
gain. The circuit has been fabricated in 65 nm CMOS technology
with an active area of just 0.09 mm2. It consumes 7.2 mA,
excluding the six phase local oscillator generation, from a 1.2 V
supply, achieving a third order harmonic rejection of 40 dB, and
a noise figure of 3 to 4.5 dB at 52 dB gain. The out of band IIP2
and IIP3 at full gain is +55 dBm and +5 dBm, respectively.
operating from 700 MHz to 3.7 GHz with 3rd order harmonic
rejection. It consists of a complementary low noise transconductance
amplifier with capacitive cross coupling and negative gm
current sources, a six phase current-mode passive mixer, and
baseband transimpedance amplifiers providing programmable
gain. The circuit has been fabricated in 65 nm CMOS technology
with an active area of just 0.09 mm2. It consumes 7.2 mA,
excluding the six phase local oscillator generation, from a 1.2 V
supply, achieving a third order harmonic rejection of 40 dB, and
a noise figure of 3 to 4.5 dB at 52 dB gain. The out of band IIP2
and IIP3 at full gain is +55 dBm and +5 dBm, respectively.
Department/s
Publishing year
2013
Language
English
Publication/Series
IEEE
Document type
Conference paper
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
IEEE European Solid State Circuits Conference, ESSCIRC 2013
Conference date
2013-09-16 - 2013-09-20
Conference place
Bucharest, Romania
Status
Published
Project
- EIT_DARE Digitally-Assisted Radio Evolution
Research group
- Analog RF