Low Power Unrolled CORDIC Architectures

Summary, in English

This paper shows a novel methodology to improve unrolled CORDIC architectures. The methodology is based on removing adder stages starting from the first stage. As an example, a 19-stage CORDIC is used but the methodology is applicable on CORDICs with an arbitrary number of stages. The CORDIC is implemented, simulated, and synthesized into hardware. In the paper, the performance is shown to be increased by 23% and that the dynamic power can be reduced by 27%.

• Author: Peter Nilsson; Yuhang Sun; Rakesh Gangarajaiah; Erik Hertz
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2015
• Language: English
• Links: http://dx.doi.org/10.1109/NORCHIP.2015.7364396
• Document type: Conference paper
• Topic: Other Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: NORSIG 2015
• Conference date: 2015-10-26
• Status: Published
• Research group: Digital ASIC