TURNUS: a Design Exploration Framework for Dataflow System Design
Author
Summary, in English
While research on the design of heterogeneous concurrent
systems has a long and rich history, a unified design methodology
and tool support has not emerged so far, and thus the creation
of such systems remains a difficult, time-consuming and error-prone
process. The absence of principled support for system evaluation and
optimization at high abstraction levels makes the quality of the resulting
implementation highly dependent on the experience or prejudices of the
designer. This is particularly critical when the combinatorial explosion
of design parameters overwhelms available optimization tools. In this
work we address these matters by presenting a unified design exploration
framework suitable for a wide range of different target platforms. The
design is unified and implemented at high level by using a standard
dataflow language, while the target platform is described using the IP-
XACT standard. This facilitates different design space heuristics that
guide the designer during validation and optimization stages without
requiring low-level implementations of parts of the application. Our
framework currently yields exploration and optimization results in terms
of application throughput and buffer size dimensioning, although other
co-exploration and optimization heuristics are available.
systems has a long and rich history, a unified design methodology
and tool support has not emerged so far, and thus the creation
of such systems remains a difficult, time-consuming and error-prone
process. The absence of principled support for system evaluation and
optimization at high abstraction levels makes the quality of the resulting
implementation highly dependent on the experience or prejudices of the
designer. This is particularly critical when the combinatorial explosion
of design parameters overwhelms available optimization tools. In this
work we address these matters by presenting a unified design exploration
framework suitable for a wide range of different target platforms. The
design is unified and implemented at high level by using a standard
dataflow language, while the target platform is described using the IP-
XACT standard. This facilitates different design space heuristics that
guide the designer during validation and optimization stages without
requiring low-level implementations of parts of the application. Our
framework currently yields exploration and optimization results in terms
of application throughput and buffer size dimensioning, although other
co-exploration and optimization heuristics are available.
Department/s
Publishing year
2013
Language
English
Publication/Series
IEEE International Symposium on Circuits and Systems
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Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Computer Science
Conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2013
Conference date
2013-05-19 - 2013-05-23
Conference place
Beijing, China
Status
Published
Research group
- ESDLAB