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A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency

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Author

Summary, in English

Abstract — The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X-axis phases and Y-axis phases (based on 2-D definition) can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90nm CMOS process and consumes 1.8mA from 1.2V. The measured input range can safely cover a full period of a 50MHz sampling signal. With the same delay elements, the latency time is less than 1/6 of that needed in a standard Vernier TDC.

Publishing year

2013

Language

English

Pages

195-206

Publication/Series

Analog Integrated Circuits and Signal Processing

Volume

76

Issue

2

Document type

Journal article

Publisher

Springer

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • GRO
  • Vernier
  • Time to digital converter
  • 2-D

Status

Published

ISBN/ISSN/Other

  • ISSN: 0925-1030