A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS

Summary, in English

Correct estimation of symbol timing, Carrier Frequency

Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial

in Orthogonal Frequency Division Multiplexing (OFDM) communication.

Typically, high estimation accuracy is desired, but often

comes with increased complexity. Which has a direct repercussion

in energy consumption. In this article, an architecture based on

Sign-Bit estimation with low complexity, and hence low power

dissipation, is presented. The architecture, is capable of estimating

the afore-mentioned parameters in virtually any OFDM

standard. The proof of concept has been fabricated in 65 nm

CMOS technology with low-power high-VT cells. Measurements

performed with supply voltage of 1.2V. resulted in a power

dissipation of 350 μW, 6 times smaller to that of an equivalent

8-bit architecture, and the lowest power density reported in

literature.

• Author: Isael Diaz; Siyu Tan; Yun Miao; Leif Wilhelmsson; Ove Edfors; Viktor Öwall
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2015
• Language: English
• Publication/Series: 2015 IEEE International Symposium on Circuits and Systems (ISCAS)
• Links: http://dx.doi.org/10.1109/ISCAS.2015.7169314
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE International Symposium on Circuits and Systems (ISCAS), 2015
• Conference date: 2015-05-24 - 2015-05-27
• Conference place: Lisbon, Portugal
• Status: Published
• Research group: Digital ASIC
• ISBN/ISSN/Other: ISBN: 978-1-4799-8391-9