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Silent CMOS circuits aiming for system-on-chip

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Author

  • Jiren Yuan

Summary, in English

A silent CMOS circuit architecture is proposed. Different silent CMOS gate solutions are presented and compared to the normal CMOS precharged gate in switching noise level. A silent 16-bit parallel carry-look-ahead adder is demonstrated. Simulation results on the circuits and the post layout of the adder are given, which shows a 10 times reduction in noise level is possible

Publishing year

2005

Language

English

Pages

278-281

Publication/Series

2005 6th International Conference on ASIC Proceedings

Volume

1

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • 16 bit
  • parallel carry look ahead adder
  • switching noise
  • system-on-chip
  • silent CMOS circuit architecture
  • noise level reduction

Conference name

2005 6th International Conference on ASIC Proceedings

Conference date

2005-10-24 - 2005-10-27

Conference place

Shanghai, China

Status

Published

ISBN/ISSN/Other

  • ISBN: 0780392108
  • ISBN: 0-7803-9210-8