An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS

Summary, in English

This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock jitter sensitivity. The measured prototype consumes 11mW from a 1.2 V power supply, and achieves an SNDR/SFDR of 63.5dB/76dB.

• Author: Xiaodong Liu; Mattias Andersson; Martin Anderson; Lars Sundstrom; Pietro Andreani
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2014
• Language: English
• Pages: 2337-2340
• Publication/Series: 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE International Symposium on Circuits and Systems (ISCAS), 2014
• Conference date: 2014-06-01 - 2014-06-05
• Conference place: Melbourne, Australia
• Status: Published
• ISBN/ISSN/Other: ISSN: 2158-1525; ISSN: 0271-4310