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Ultra Low Power Error Correction Circuits- Technology Scaling and Sub-Vt operation

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Author

Summary, in English

echniques are evaluated for implementing error- correction codes (ECC) in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VT analog decoding techniques. Novel sub-VT digital designs are proposed and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub- VT implementation is predicted to offer 29× gain in power consumption for a (3,6) LDPC decoder of length N = 512 operating at a throughput of 200Mbps, compared to standard digital implementation of the same design.

Publishing year

2012

Language

English

Pages

913-917

Publication/Series

IEEE Transactions on Circuits and Systems II: Express Briefs

Volume

59

Issue

12

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Error correction codes
  • sub-threshold
  • ultra-low voltage
  • analog decoders
  • biomedical implants

Status

Published

Research group

  • Digital ASIC
  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISSN: 1549-7747