Efficient Processing and Storage for Massive MIMO Digital Baseband
Author
Summary, in English
This thesis focuses on two important topics in digital baseband processing: energy-efficient computing and organization of large matrices. System algorithm-circuit co-optimization is explored to meet the real-time computational requirements. In the first topic, the concept of adaptive energy-quality scalable circuit is studied to trade between Quality of Service (QoS) and energy consumption. At circuit design level, a multiplier supporting three wordlengths is designed to provide run-time processing precision adjustment. At system and algorithm level, the concept of algorithm switching is investigated. A resource scheduling scheme to switch between accurate and approximative algorithms is developed to exploit the dynamics in the wireless channel. As shown in a case study, 58% energy can be saved by applying this method when implementing on a QR-decomposition processor. In terms of data organization, the concept of parallel memories is applied to provide low-latency, high-bandwidth, and highly flexible data access for massive MIMO baseband processing. On top of this, on-chip channel data compression methods are proposed, which utilize the inherent sparsity in massive MIMO channel. As a case study, the presented algorithms are capable of saving about 75% of storage requirement for a 128-antenna system with less than 0.8dB loss in performance. Based on the channel compression concept and various access patterns supplied by parallel memories, a heterogeneous memory system is designed and implemented (layout) using ST 28nm Fully Depleted Silicon On Insulator (FD-SOI). The area cost is 0.47mm2, which is 58% smaller than a memory system with the same capacity and without compression.
The energy-efficient computing and data organization of large matrices provides a promising methodology for the actual deployment of massive MIMO baseband processor.
Department/s
Publishing year
2018
Language
English
Full text
Document type
Dissertation
Publisher
Department of Electrical and Information Technology, Lund University
Topic
- Engineering and Technology
Keywords
- digital signal processor
- baseband processing
- parallel memories
- data compression
- channel sparsity
- Reconfigurable computing
- QR decomposition
- resource scheduling
- massive MIMO
- MIMO
- DVFS
Status
Published
Research group
- Integrated Electronic Systems
Supervisor
ISBN/ISSN/Other
- ISBN: 978-91-7753-562-1
- ISBN: 978-91-7753-561-4
Defence date
23 March 2018
Defence time
10:15
Defence place
lecture hall E:1406, Ole Römers väg 3, Lund University, Faculty of Engineering LTH, Lund
Opponent
- Andreas Burg (Professor)