Dynamically Reconfigurable Architectures for Real-time Baseband Processing
Author
Summary, in English
To achieve a balance between the aforementioned design requirements, a coarse-grained dynamically reconfigurable cell array architecture is proposed. The architecture is constructed from an array of heterogeneous function units interconnected through a hierarchical on-chip network. The adopted in-cell configuration scheme enables fast context switching between standards and between computational tasks during run-time. Although cell array is a generic hardware platform, this thesis focuses on the architectural development of the cell array tailored specifically for digital baseband processing of contemporary wireless communication systems. Various degrees of flexibilities among operating scenarios, algorithms, tasks, and supporting standards are exploited. Besides, high hardware efficiency is attained by conducting algorithm-architecture, hardware-software, and processing-memory co-design.
In this thesis, flexibility, performance and efficiency of the proposed architecture are demonstrated through two case studies. First, the cell array is deployed in a digital front-end receiver, aiming to support concurrent processing of multiple radio standards, 3GPP Long Term Evolution (LTE), IEEE 802.11n, and Digital Video Broadcasting for Handheld (DVB-H). Dynamic configuration of the cell array enables run-time switching between different operation modes, multi-standard single-stream and multi-standard multi-stream, in order to maximize hardware usage for attaining high computational performance while sufficing current processing demands. Implementation results show that the immense flexibility offered by the cell array comes at the cost of only about 16% area overhead in comparison to its ASIC counterpart. In the second study, the cell array architecture is extended with extensive vector computing capabilities, aiming to perform high-throughput MIMO signal processing. As an illustration, three computationally intensive blocks, namely channel estimation, pre-processing, and symbol detection, of a 4x4 MIMO processing chain in a 20 MHz 64-QAM 3GPP LTE-Advanced downlink are mapped and processed in real-time. With 6 processing and 10 memory cells deployed in the array, the achieved system throughput is 368 Mb/s at 500 MHz and the corresponding energy consumption for processing one information bit is 1.49 nJ/b. Compared to state-of-the-art implementations, the proposed solution outperforms related programmable platforms by up to 6 orders of magnitude in energy efficiency, and is 1.7-13.6 and 1.4-15 times less efficient than ASICs in terms of area and energy, respectively, when performing each individual task.
Department/s
Publishing year
2014
Language
English
Full text
Document type
Dissertation
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- Reconfigurable Computing
- Coarse-Grained Architecture
- Dynamic Reconfiguration
- SIMD
- VLIW
- ASIP
- Vector Processor
- Baseband Processing
- OFDM
- MIMO
- Channel Estimation
- Symbol Detection.
Status
Published
Project
- High Performance Embedded Computing
- EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
Research group
- Digital ASIC
Supervisor
ISBN/ISSN/Other
- ISBN: 978-91-7473-974-9
Defence date
27 May 2014
Defence time
10:15
Defence place
Lecture hall E:1406, Department of Electrical and Information Technology, Ole Römers väg 3, Lund University Faculty of Engineering
Opponent
- Bjorn De Sutter (Professor)