A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process

Summary, in English

A 2.8-to-5.8GHz VCO designed in a 28nm UTBB FD-SOI CMOS process adopts a reconfigurable active core to save power at the lower oscillation frequencies, and to enable a trade-off between power consumption and phase noise at all frequencies. The UTBB FD-SOI CMOS process is instrumental to achieve a tuning range in excess of one octave at low power consumption, while the use of an 8-shaped tank coil yields a VCO that is highly insensitive to external magnetic fields. The VCO operates from 0.9V and has a figure-of-merit of 186-189 dBc/Hz, depending on the oscillation frequency and the configuration of the oscillator core. The active area of the VCO is 380 μm × 700 μm.

• Author: Luca Fanori; Ahmed Mahmoud; Thomas Mattsson; Peter Caputa; Sami Rämö; Piero Andreani
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2015
• Language: English
• Pages: 195-198
• Publication/Series: 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
• Links: http://dx.doi.org/10.1109/RFIC.2015.7337738
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: UTBB FD-SOI; CMOS; reconfigurable core; VCO; one octave; class-B; low phase noise
• Conference name: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015
• Conference date: 2015-05-17 - 2015-05-19
• Conference place: Phoenix, Arizona, United States
• Status: Published
• ISBN/ISSN/Other: ISBN: 978-1-4799-7642-3