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A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter

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Author

Summary, in English

A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65 nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2 V in a single stage, and has a static power consumption of 640 pW at a 0.12 to 1 V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72 MHz was observed at 0.3 to 1 V conversion.

Publishing year

2014

Language

English

Pages

990-993

Publication/Series

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • level-converter
  • level-shifter
  • ULV
  • ultra low power
  • ultra low voltage
  • single stage

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS), 2014

Conference date

2014-06-01 - 2014-06-05

Conference place

Melbourne, Australia

Status

Published

ISBN/ISSN/Other

  • ISSN: 0271-4310
  • ISSN: 2158-1525