Pushing the limits of standard CMOS

Summary, in English

An improved clocking scheme and sharper circuit design and logic selection, which have yielded a five-to-tenfold increased in the speed of standard CMOS ICs, are discussed. The clocking strategy relies on a true single-phase clock, device sizes are varied to optimize their speed, and a precharged logic style reduces capacitive loads. The tradeoff is roughly a doubling of circuit area. The high-speed CMOS technique has been demonstrated experimentally, with good results. For example, ripple counters in 3 and 2 μm CMOS processes reached input frequencies of 400 and 750 MHz, respectively, or nearly 80 and 70% of the intrinsic speeds of these processes. Pipelined accumulators in 2 and 1.2 μm CMOS processes operated at up to 430 and 700 MHz clock frequencies, respectively. The data rate of an error correcting encoder designed for an optical fiber communication link was measured as 1.2 Gb/s, while the corresponding decoder was simulated at the same speed. In general, the circuits were found to be as robust as CMOS circuits designed in a conventional way

• Author: Jiren Yuan; Christer Svensson
• Publishing year: 1991
• Language: English
• Pages: 52-53
• Publication/Series: IEEE Spectrum
• Volume: 28
• Issue: 2
• Links: http://dx.doi.org/10.1109/6.100912
• Document type: Journal article
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• ISBN/ISSN/Other: ISSN: 0018-9235