Implementation of a Novel Architecture for DFT-based Channel Estimators in OFDM Systems
Author
Summary, in English
A new architecture for Discrete Fourier Transform (DFT) based channel estimation has been analyzed, implemented and synthesized for ASIC. The core concept of the proposed esti- mation algorithm is to process the channel increments rather than the channel coefficients. With strong enough time correlation, we can reduce the wordlength of processing blocks compared to standard channel estimators and hence the resulting area and power. We provide an analytical tool to predict the potential gains in bit reduction for different mobility scenarios. Our simulations show that the wordlength can be reduced from 9 to 3 bits when operating in low mobility scenarios, with 5Hz Doppler frequency, while maintaining acceptable performance. Synthesis results show up to 40% reduction in area, compared to the original DFT-based approach, in a 65nm CMOS process.
Department/s
Publishing year
2014
Language
English
Publication/Series
[Host publication title missing]
Full text
- Available as PDF - 384 kB
- Download statistics
Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
SIPS 2014
Conference date
2014-10-20
Status
Published