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A low-power 2nd-order CT delta-sigma modulator with an asynchronous SAR quantizer

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Author

Summary, in English

This paper presents a low voltage continuous-time delta-sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 W from a 800 mV power supply.

Publishing year

2015

Language

English

Pages

409-420

Publication/Series

Analog Integrated Circuits and Signal Processing

Volume

84

Issue

3

Document type

Journal article

Publisher

Springer

Topic

  • Signal Processing

Keywords

  • Delta-sigma
  • Asynchronous SAR
  • Single operational amplifier
  • Low-power
  • Continuous time

Status

Published

ISBN/ISSN/Other

  • ISSN: 0925-1030