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Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

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Author

Summary, in English

Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

Publishing year

2012

Language

English

Pages

442-447

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Test Scheduling
  • 3D stacked IC
  • JTAG
  • Test Architecture
  • Through Silicon Via

Conference name

2012 25th International Conference on VLSI Design

Conference date

2012-01-07

Conference place

Hyderbad, India

Status

Published

Research group

  • Digital ASIC