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Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster

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Author

Publishing year

2011

Language

English

Publication/Series

European Test Symposium (ETS11), Trondheim, Norway, May 23-27, 2011., 2011

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE European Test Symposium (ETS), 2011

Conference date

2011-05-23 - 2011-05-27

Conference place

Trondheim, Norway

Status

Published

Research group

  • Digital ASIC